1. Field of the Invention
The present invention relates to a power semiconductor device and a fabrication method thereof, and more particularly, to a power semiconductor device which has a high breakdown voltage structure using semi-insulating polycrystalline silicon, and a fabrication method thereof.
2. Description of the Related Art
With a recent trend toward large-sized and large capacity application apparatuses, a power semiconductor device having a high breakdown voltage, a high current capacity, and high speed switching characteristics has become necessary.
A power semiconductor device requires a low saturation voltage, particularly, to reduce power loss in a conductive state while flowing a significant amount of current. Also, the power semiconductor device fundamentally requires high breakdown voltage characteristics, such as a property that the power semiconductor device can sustain a high reverse voltage applied to both ends of the power semiconductor device when or at the moment when a switch is turned off. The power semiconductor device requires various high breakdown voltages from tens to thousands of volts according to its application.
Meanwhile, the breakdown voltage of the semiconductor device is determined by a depletion region formed in a PN junction, since the voltage applied to the PN junction is mostly applied to the depletion region. It is known that the breakdown voltage is affected by the curvature of the depletion region. That is, in a planar junction, the electric field is concentrated more on an edge of a junction portion having a large curvature than on a flat portion thereof, due to an electric field crowding effect. Thus, an avalanche breakdown easily occurs at the edge, and the breakdown voltage of the entire depletion region is reduced.
Accordingly, several technologies have been proposed to prevent the concentration of the electric field on the edge of the junction portion. The first one is forming a field plate (FP) on a substrate of a field region adjacent to the edge of the planar junction. The second one is forming a field limiting ring (FLR), being an impurity layer having the same conductive type as the junction portion, in the substrate of the field region. The third one is combining the first and second technologies.
A method of forming a semi-insulating polycrystalline silicon (SIPOS) film on a substrate in which a planar junction is formed, which is introduced in an article published in the early 1970's, has been continuously developed together with these technologies. The technology of manufacturing a high breakdown voltage semiconductor device using the SIPOS film can further reduce the area of a chip by about 10 to 20% compared to other technologies, and can obtain a stable breakdown voltage.
FIG. 1 is a cross-section of a high breakdown voltage transistor formed using a conventional SIPOS film.
Referring to FIG. 1, a base region 4 having a second conductivity type is formed on a collector region 2 having a first conductivity type, and an emitter region 6 having the first conductivity type is formed in the base region 4. A field limiting ring 8 for preventing an electric field from being concentrated on the edge of a junction between the collector region 2 and the base region 4 is formed a predetermined distance apart from the edge of the base region 4. A first conductive channel stop region 10 for isolation is formed in a field region spaced a predetermined distance apart from the field limiting ring 8.
In addition to the field limiting ring 8, An SIPOS film 12 for preventing concentration of the electric field on the edge of the junction, and an oxide film 14 are sequentially deposited on the semiconductor substrate. A base electrode 16, an emitter electrode 18, and an equipotential electrode 20 are formed, and a collector electrode 22 is formed on the bottom surface of the collector region 2.
At the "Third International Symposium on Power Semiconductor Devices and ICs" (in 1991), T. Stockmeler et al. applied and developed such a structure into a power diode structure which uses a technique for extending a junction edge portion instead of a field limiting ring, and uses a nitride film instead of an oxide film.
However, in such a structure, a remarkably large amount of reverse leakage current flows since the SIPOS film 12 is deposited directly on the semiconductor substrate. Thus, problems occur when actually applying this structure.
FIG. 2 is a cross-section of another power semiconductor device using a conventional SIPOS film. The same reference numerals as those in FIG. 1 denote the same elements, so they will not be described again.
Referring to FIG. 2, an oxide film 24 grown by thermal oxidation is first formed on a semiconductor substrate, and two SIPOS films 26 and 28 are deposited on the resultant structure. The first SIPOS film 26 on the oxide film 24 has an oxygen concentration of about 12%, and the second SIPOS film 28 has an oxygen concentration of about 25 to 30%. Thus, the surface is protected, and simultaneously a greater field plate effect can be provided than when the oxide film or nitride film is used.
However, when the SIPOS film is deposited in-situ twice, it is difficult to accurately control the thickness of the film or the concentration of oxygen. Therefore, determination of whether desired first and second SIPOS films are actually deposited is not possible during the process, thus difficult process management is expected. Also, the SIPOS film has a large scattering with respect to the high breakdown voltage, since it does not perform well under humid conditions. Furthermore, in the oxide film 24 deposited below the SIPOS film, the oxide film on the emitter region is 5,000 to 10,000 .ANG. thick, the oxide film on the base region is 10,000 to 20,000 .ANG. thick, and the oxide film on the field region is 15,000 to 30,000 .ANG. thick. Thus, when the oxide film is dry etched in an etch process for forming a contact after forming the SIPOS film, the costs are high, and productivity of dry etch equipment is degraded.